The present invention relates to a pattern synchronizing circuit which is used, for example, in measurement of the error rate of a digital signal transmission system, for synchronizing a reference pattern generator with input test data (a pseudo random pattern) prior to the measurement. More particularly, the invention pertains to a demultiplexed pattern synchronizing circuit whereby parallel sequences of input data obtained by demultiplexing a high-speed pseudo random pattern are synchronized with parallel sequences of reference patterns.
In the case of measuring the transmission error rate of a digital signal transmission system, a measurement pattern formed by a repetition of a certain pattern of a predetermined bit length is provided from a pattern generator to the digital transmission system at the transmitting side thereof. At the receiving side of the digital transmission system the same pattern as the measurement pattern at the transmission side is generated as a reference pattern and compared, bit by bit, with an input pattern provided through the transmission system and containing errors, by which the errors in the input pattern are detected, and the number of errors per unit bit is counted. It is customary to use, as the measurement pattern, a pseudo random pattern, usually a repetitive pattern of a maximum length linear shift register sequence of a (2.sup.n -1)-bit length. The bit length of a non-repetitive or random maximum length pattern, obtainable with an n-stage shift register, is 2.sup.n -1, and such a pattern is called a maximum length linear shift register sequence. It is well-known in the art that the pseudo random pattern, which is a repetition of such a pattern, has a feature in that a sequence of bits extracted therefrom every N=2.sup.a (where a is an integer equal to or greater than 1) bit positions starting at an arbitrary bit position constitutes the same pattern as the original pseudo random pattern.
In the case of measuring the error rate of a transmission system when a digital signal is provided thereto at a high speed, it is difficult to implement a high-speed comparator which is able to compare the input pattern with the reference pattern on a bitwise basis at the receiving side. A conventional solution to this problem, which takes advantage of the above-mentioned feature of the maximum length linear shift register sequence (hereinafter referred to as ML sequence), is to divide the input pattern, bit by bit, into N=2.sup.a parallel sequences on N lines. That is, the input pattern is demultiplexed into N parallel sequences of low-speed data at the receiving side. In this instance, if the received pattern is error-free, the N=2.sup.a parallel sequences of low-speed data each form the same pattern as the high-speed pseudo random pattern for measurement use generated at the transmitting side and they are sequentially displaced a fixed number of bits (about 1/N of the pattern period) apart in phase. Accordingly, similar N parallel sequences of low-speed patterns are generated as reference patterns at the receiving side and are respectively compared with the demultiplexed N parallel sequences of low-speed data, by which the error rate of the digital transmission system can be measured. For correct measurement of the error rate, however, it is necessary to establish synchronization between the N demultiplexed parallel sequences of low-speed data and the N parallel sequences of reference patterns so that they are in phase with each other.
Such a demultiplexed pattern synchronizing circuit is disclosed in U.S. Pat. No. 4,878,233. This U.S. patent shows a case where high-speed input data is demultiplexed, by use of a high-speed clock synchronized therewith, into four parallel sequences of low-speed data on four output lines for comparison with four parallel sequences of reference patterns by four comparators. The four parallel sequences of reference patterns are each generated in synchronization with a low-speed clock obtained by frequency dividing the above-said high-speed clock down to 1/4. The number of disagreements in the results of comparison by the four comparators is counted. When the count value exceeds a predetermined value, it is decided that the four parallel sequences of low-speed data and the four parallel sequences of reference patterns are not synchronized with each other. Thereafter, upon each counting of a predetermined number of disagreements, one of the low-speed clocks for generating the reference patterns is eliminated, by which the four parallel sequences of reference patterns are all delayed by one bit relative to corresponding four parallel sequences of low-speed data. The one-bit delay of the reference patterns is repeated until the four parallel sequences of reference patterns are synchronized with the four parallel sequences of low-speed data.
With the demultiplexed pattern synchronizing circuit set forth in the above-mentioned U.S. patent, however, no synchronization can be established, in the worst case, until the reference pattern is delayed for a period of time equal to the length of the ML sequence minus one bit, i.e. (2.sup.n -1)-1 bit (which is approximately one reference pattern period in practice, because n is selected equal to or greater than 4). In addition, the time length of 2.sup.n -1 bits in the reference pattern (or low-speed data) is equal to the time length of 4.times.(2.sup.n -1) bits in the high-speed input data, and this corresponds to approximately four periods of the maximum length linear shift register sequence which is repeated in the high-speed input data. In other words, about four periods of the high-speed pattern for measurement are consumed merely for synchronization, not for measurement of the error rate. The impairs the efficiency of measurement of the error rate. Recently, in particular, a high-speed digital transmission in the gigahertz band for optical communication has come into use. The pattern for measuring the error rate of such a high-speed digital transmission system is required to be large in the bit length of one pattern period.
For example, in the case where the number of bits of one period of the ML sequence of the high-speed pattern data for measurement is 2.sup.23 -1, the frequency f is 2 GHz and the number N of parallel sequences of low-speed data is 16, then one period of the reference pattern becomes approximately 67 milliseconds. In the case where the number of bits of one period of the ML sequence is 2.sup.31 -1, the frequency f is 2 GHz and the number N is 16, one period of the reference pattern becomes about 17 seconds. Thus, when the bit length of one period of the measurement pattern (high-speed input data) is as large as 2.sup.31 -1 (.perspectiveto.2.15.times.10.sup.9) bits, the time for synchronization is 17 seconds at maximum and hence is impractical.